Imaging in proton-based radiotherapy can be advanced by the full characterisation of the thermoacoustic signal generated after the deposition of the proton beam energy into the absorber material. This paper presents an 8-bit 20M Samples Per Second fully differential Successive Approximation Register designed in 28nm CMOS for new generation Proton Sound Detectors. The specifications of the converter are determined by the low amplitude, high frequency and non-periodicity of the thermoacoustic signal, and by the electrical requirements of the detector acquisition chain. The proposed converter achieves, in nominal conditions, a Signal to Noise Ratio of 48.07, corresponding to an Equivalent Number Of Bits of 7.69, near ideal differential and integral non-linearity, and a total power consumption of $160.98\mu W$. The circuit is designed to be robust to Process- Voltage-Temperature variations being able to achieve a worst-case-scenario Equivalent Number Of Bits of 7.42, and to mismatch suffering a maximum full-scale voltage reduction of $3LSB$.
Turossi, D., Vallicelli, E., De Matteis, M., Di Meo, G., D'Ottavi, F., Baschirotto, A. (2024). A 7.69 ENOB, 161uW SAR ADC in 28nm CMOS for Proton Sound Detectors. In 2024 19th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2024 (pp.1-4). IEEE [10.1109/prime61930.2024.10559698].
A 7.69 ENOB, 161uW SAR ADC in 28nm CMOS for Proton Sound Detectors
Turossi, Davide
Primo
;Vallicelli, Elia ArturoSecondo
;De Matteis, MarcelloPenultimo
;Baschirotto, AndreaUltimo
2024
Abstract
Imaging in proton-based radiotherapy can be advanced by the full characterisation of the thermoacoustic signal generated after the deposition of the proton beam energy into the absorber material. This paper presents an 8-bit 20M Samples Per Second fully differential Successive Approximation Register designed in 28nm CMOS for new generation Proton Sound Detectors. The specifications of the converter are determined by the low amplitude, high frequency and non-periodicity of the thermoacoustic signal, and by the electrical requirements of the detector acquisition chain. The proposed converter achieves, in nominal conditions, a Signal to Noise Ratio of 48.07, corresponding to an Equivalent Number Of Bits of 7.69, near ideal differential and integral non-linearity, and a total power consumption of $160.98\mu W$. The circuit is designed to be robust to Process- Voltage-Temperature variations being able to achieve a worst-case-scenario Equivalent Number Of Bits of 7.42, and to mismatch suffering a maximum full-scale voltage reduction of $3LSB$.File | Dimensione | Formato | |
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