500 MHz CMOS 28-nm Floating Point Arithmetic Unit for 32-Bit RISC-V Microprocessors

This work presents the design and implementation of a single-precision 32-bit floating point unit (FPU) in 28-nm bulk CMOS technology. The FPU includes arithmetic operations compliant with the RISC-V instruction set architecture, allowing the definition of the rounding method and exceptions defined by the standard. The included floating point (FP) operations are addition, multiplication, division, and square root, which require, respectively, 7, 14, 15 and 44 clock cycles. A denormalized FP input causes an overhead of 2 clock cycles in each case except for the multiplication, where the overhead is 5. Each operation is based on a respective 24-bit integer version that works on the fractional part of the number. For the computation of the FP result, the integer operators share the common stages of input preparation and output rounding and normalization. The multiplier is based on the Dadda multiplier architecture, the divider implements the radix-16 digit recurrence division algorithm, and the square root algorithm used is the Mr. Woo's abacus algorithm. The FPU has been synthesized both on a Xilinx Spartan-7 XC7S25 FPGA and in TSMC CMOS 28-nm HPC+ technology by 55k gates in an area of 40 μm2 and 5,32 μW of dynamic power and 0,03 μW of static power consumption. The behavioral code is publicly available.