A 55nm, Multiple-Loop, Fast-Transient, −76.2 dB Worst-Case PSRR LDO for High-End Audio Circuits

A low dropout regulator (LDO) is designed in 55nm CMOS technology. It is targeted for high-end audio applications, which present continuous-time as well as switched-capacitor building blocks. A multiple loop capacitor-less structure is pro- posed to cope with both high power supply rejection ratio (PSRR) and fast transient response. In particular, a folded flipped voltage follower (FFVF) output buffer presents a fast inner loop, needed to detach the error amplifier (EA) from the load capacitor (CL) and drive this latter under fast transients. A variable resistance and adaptive biasing are developed to guarantee stability under all load conditions, including IL = 0. Moreover, a slower high- gain loop is designed to set the output potential Vout, further reducing the output impedance and improving the PSRR, line and load regulation. The proposed LDO is implemented using IO high threshold transistors and provides an output voltage Vout = 1 V from a 1.2 V 10% supply with a minimum possible dropout (V min drop ) of 80 mV. It achieves a worst-case low-frequency PSRR of -76.2 dB under Montecarlo simulations (MC) and a recovery time of 142 ns when a load spike of 800 ?A is applied. Line and load regulation are 0.001 mV/V and 0.007 mV/mA. Moreover, the quiescent current (Iq ) is less than 20 ?A at maximum IL. © 2024 IEEE.