This paper presents the complete transistor-level design of a Low-Noise-Amplifier (LNA) in CMOS 28 nm bulk technology for sensing the weak extracellular neuro-potentials signals in Electrolyte-Oxide-MOS (EOMOS) Brain-Chip Interfaces. The proposed LNA adopts an efficient pseudo-resistor topology that allow to synthesize a stable resistance (in the tens of {G} order) without any external calibration. The LNA has 2.4 Hz minimum passband frequency performing 7.8 {V}_{RMS and 8.8mu {V}_{RMS input-referred noise power at 1 Hz - 300 Hz (Local Field Potential) and 300 Hz-5 kHz (Action Potentials) bandwidth, respectively. The device consumes 2.4 {W} power and has been designed in 28 nm CMOS technology.
Vallicelli, E., Baschirotto, A., Stevenazzi, L., Rota, L., De Matteis, M. (2022). 2.4 Hz-5 kHz Passband 11.8mu {V}_{RMS Noise Power Neural Amplifier for Brain-Chip Interfaces. In 2021 28th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2021 - Proceedings. IEEE [10.1109/ICECS53924.2021.9665636].
2.4 Hz-5 kHz Passband 11.8mu {V}_{RMS Noise Power Neural Amplifier for Brain-Chip Interfaces
Vallicelli E. A.;Baschirotto A.;Stevenazzi L.;Rota L.;De Matteis M.
2022
Abstract
This paper presents the complete transistor-level design of a Low-Noise-Amplifier (LNA) in CMOS 28 nm bulk technology for sensing the weak extracellular neuro-potentials signals in Electrolyte-Oxide-MOS (EOMOS) Brain-Chip Interfaces. The proposed LNA adopts an efficient pseudo-resistor topology that allow to synthesize a stable resistance (in the tens of {G} order) without any external calibration. The LNA has 2.4 Hz minimum passband frequency performing 7.8 {V}_{RMS and 8.8mu {V}_{RMS input-referred noise power at 1 Hz - 300 Hz (Local Field Potential) and 300 Hz-5 kHz (Action Potentials) bandwidth, respectively. The device consumes 2.4 {W} power and has been designed in 28 nm CMOS technology.
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