A graphical tool to assess spatial patterns of defectivity on semiconductor wafers: an approach based on the minimum spanning tree algorithm

Semiconductor industry is beginning to play an essential role in the economy of modern society as well as in the day-to-day life of humans. In this industrial sector, one of the main causes of yield loss is the presence of defects on the wafer surface. A prompt identification of the causes of such clusters, as well as their early elimination, is therefore critical. In this paper, we present an explorative method to detect the presence of systematic spatial structures in the defect locations occurring on the wafer surface, based on the minimum spanning tree algorithm. The proposed procedure proved to be effective in detecting both convex and non-convex-shaped clusters of defects, both on simulated data and in a real wafer data application