The CLARO-CMOS is an application specific integrated circuit (ASIC) designed for fast photon counting with pixellated photodetectors such as multi-anode photomultiplier tubes (Ma-PMT), micro-channel plates (MCP), and silicon photomultipliers (SiPM). The first prototype has four channels, each with a charge sensitive amplifier with settable gain and a discriminator with settable threshold, providing fast hit information for each channel independently. The design was realized in a long-established, stable and inexpensive 0.35 μm CMOS technology, and provides outstanding performance in terms of speed and power dissipation. The prototype consumes less than 1 mW per channel at low rate, and less than 2 mW at an event rate of 10 MHz per channel. The recovery time after each pulse is less than 25 ns for input signals within a factor of 10 above threshold. Input referred RMS noise is about 7.7 ke− (1.2 fC) with an input capacitance of 3.3 pF. With this value of input capacitance a timing resolution down to 10 ps RMS was measured for pulser signals of a few million electrons, corresponding to the single photon response for these detectors

Carniti, P., DE MATTEIS, M., Giachero, A., Gotti, C., Maino, M., Pessina, G. (2012). CLARO-CMOS, a very low power ASIC for fast photon counting with pixellated photodetectors. JOURNAL OF INSTRUMENTATION, 7(11), 11026-11049 [10.1088/1748-0221/7/11/P11026].

CLARO-CMOS, a very low power ASIC for fast photon counting with pixellated photodetectors

CARNITI, PAOLO;DE MATTEIS, MARCELLO;GIACHERO, ANDREA;GOTTI, CLAUDIO
;
MAINO, MATTEO;Pessina, G.
2012

Abstract

The CLARO-CMOS is an application specific integrated circuit (ASIC) designed for fast photon counting with pixellated photodetectors such as multi-anode photomultiplier tubes (Ma-PMT), micro-channel plates (MCP), and silicon photomultipliers (SiPM). The first prototype has four channels, each with a charge sensitive amplifier with settable gain and a discriminator with settable threshold, providing fast hit information for each channel independently. The design was realized in a long-established, stable and inexpensive 0.35 μm CMOS technology, and provides outstanding performance in terms of speed and power dissipation. The prototype consumes less than 1 mW per channel at low rate, and less than 2 mW at an event rate of 10 MHz per channel. The recovery time after each pulse is less than 25 ns for input signals within a factor of 10 above threshold. Input referred RMS noise is about 7.7 ke− (1.2 fC) with an input capacitance of 3.3 pF. With this value of input capacitance a timing resolution down to 10 ps RMS was measured for pulser signals of a few million electrons, corresponding to the single photon response for these detectors
Articolo in rivista - Articolo scientifico
Front-end electronics for detector readout; VLSI circuits; Analogue electronic circuits; Pixilated detectors and associated VLSI electronics
English
2012
7
11
11026
11049
none
Carniti, P., DE MATTEIS, M., Giachero, A., Gotti, C., Maino, M., Pessina, G. (2012). CLARO-CMOS, a very low power ASIC for fast photon counting with pixellated photodetectors. JOURNAL OF INSTRUMENTATION, 7(11), 11026-11049 [10.1088/1748-0221/7/11/P11026].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10281/45860
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