The present invention relates to microelectronic components, in particular CMOS circuits, which comprise, integrated in its structure, thermoelectric cooling elements exploiting the Seebeck/Peltier effect based on nanowires (1) of conductor or semiconductor material having high Seebeck coefficient, parallel and isolated from one another and organized according to a packing structure (2) which develops vertically and longitudinally and which comprises: a) superimposed alternating layers of a first dielectric material (3) which can be deposited in films of thickness less than or equal to 50 nm and etchable by a solution of a chemical compound and a second dielectric material (4) with low thermal conductivity non-etchable by said solution; b) parallel grooves (5) of retreat of the respective front of attack by the etching solution of the layers of said first dielectric material (3) on the sides of said structure which develops longitudinally; c) residues of filiform conductor or semiconductor material filling said parallel grooves (4c) constituting said parallel nanowires (1) of conductor or semiconductor material. The invention also relates to alternative processes of realization of such microelectronic components.

Narducci, D., Cerofolini, G. (2011)Microelectronic components, in particular cmos circuits, comprising thermoelectric cooling elements exploiting the seebeck/peltier effect, integrated in their structure. . Brevetto No. IT2011RM00472 20110909.

Microelectronic components, in particular cmos circuits, comprising thermoelectric cooling elements exploiting the seebeck/peltier effect, integrated in their structure

NARDUCCI, DARIO;
2011

Abstract

The present invention relates to microelectronic components, in particular CMOS circuits, which comprise, integrated in its structure, thermoelectric cooling elements exploiting the Seebeck/Peltier effect based on nanowires (1) of conductor or semiconductor material having high Seebeck coefficient, parallel and isolated from one another and organized according to a packing structure (2) which develops vertically and longitudinally and which comprises: a) superimposed alternating layers of a first dielectric material (3) which can be deposited in films of thickness less than or equal to 50 nm and etchable by a solution of a chemical compound and a second dielectric material (4) with low thermal conductivity non-etchable by said solution; b) parallel grooves (5) of retreat of the respective front of attack by the etching solution of the layers of said first dielectric material (3) on the sides of said structure which develops longitudinally; c) residues of filiform conductor or semiconductor material filling said parallel grooves (4c) constituting said parallel nanowires (1) of conductor or semiconductor material. The invention also relates to alternative processes of realization of such microelectronic components.
CPU cooling; Peltier effect; CMOS
Electricity
English
Rilevanza internazionale
7-set-2011
IT2011RM00472 20110909
Altro titolare
none
Narducci, D., Cerofolini, G. (2011)Microelectronic components, in particular cmos circuits, comprising thermoelectric cooling elements exploiting the seebeck/peltier effect, integrated in their structure. . Brevetto No. IT2011RM00472 20110909.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10281/43288
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