Power consumption of high-speed low-resolution ADCs can be reduced by means of calibration. However, this solution presents some drawbacks like allocating a calibration time, calibration algorithm complexity, calibration circuit implementation, etc. In alternative, this paper presents a 5-bit 1 Gs/s ADC without calibration, realized in a 90 nm-CMOS. The device is based on the use of an improved version of double tail dynamic comparators, operating with a fixed bias current. These comparators present a reduced kickback noise, allowing increasing the input transistors sizes in order to improve the matching. The ADC current consumption is equal to 6.9 mA from a 1.2 V supply
D’Amico, S., Cocciolo, G., DE MATTEIS, M., Baschirotto, A. (2011). A 6.9mA 5bits 90nm 1Gs/s ADC withouth calibration. MICROELECTRONICS JOURNAL, 42(2), 325-329 [10.1016/j.mejo.2010.11.006].
A 6.9mA 5bits 90nm 1Gs/s ADC withouth calibration
DE MATTEIS, MARCELLO;BASCHIROTTO, ANDREA
2011
Abstract
Power consumption of high-speed low-resolution ADCs can be reduced by means of calibration. However, this solution presents some drawbacks like allocating a calibration time, calibration algorithm complexity, calibration circuit implementation, etc. In alternative, this paper presents a 5-bit 1 Gs/s ADC without calibration, realized in a 90 nm-CMOS. The device is based on the use of an improved version of double tail dynamic comparators, operating with a fixed bias current. These comparators present a reduced kickback noise, allowing increasing the input transistors sizes in order to improve the matching. The ADC current consumption is equal to 6.9 mA from a 1.2 V supply
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