In this paper a 8.2MHz-f @-3dB bandwidth Filter-&-Amplifier to be embedded in a DVB-T RX chain is presented. The filter has been integrated in 65nm CMOS node, working with a V DD/V TH ratio (supply/threshold voltage) as low as 2. Operating point issues due to low V DD/V TH ratio has been resolved by a proper bias circuit. Since such bias circuit is part of the filter circuit, its impact on filter performance have been studied and considered in the design. Power consumption is minimized by using a novel algorithm based on Matlab procedure, which guarantees the minimum power consumption for a given transfer function, noise and linearity requirements. The device consumes 1.3mW from a single 1.2V supply voltage, features -10dBm-IIP3 at 32dB pass-band Gain, and 1.6mV rms output integrated noise over the pass-band (300kHz÷8.2MHz). © 2011 IEEE.

DE MATTEIS, M., Cocciolo, G., De Blasi, M., Baschirotto, A. (2011). A 1.3mW CMOS 65nm 4^th order 52dB-DR continuous-time analog filter for DVB-T receivers. In Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on (pp.21-24) [10.1109/ICECS.2011.6122204].

A 1.3mW CMOS 65nm 4^th order 52dB-DR continuous-time analog filter for DVB-T receivers

DE MATTEIS, MARCELLO;BASCHIROTTO, ANDREA
2011

Abstract

In this paper a 8.2MHz-f @-3dB bandwidth Filter-&-Amplifier to be embedded in a DVB-T RX chain is presented. The filter has been integrated in 65nm CMOS node, working with a V DD/V TH ratio (supply/threshold voltage) as low as 2. Operating point issues due to low V DD/V TH ratio has been resolved by a proper bias circuit. Since such bias circuit is part of the filter circuit, its impact on filter performance have been studied and considered in the design. Power consumption is minimized by using a novel algorithm based on Matlab procedure, which guarantees the minimum power consumption for a given transfer function, noise and linearity requirements. The device consumes 1.3mW from a single 1.2V supply voltage, features -10dBm-IIP3 at 32dB pass-band Gain, and 1.6mV rms output integrated noise over the pass-band (300kHz÷8.2MHz). © 2011 IEEE.
paper
CMOS fourth order-DR continuous-time analog filter; CMOS node; DVB-T RX chain; DVB-T receivers; bandwidth 8.2 MHz; bias circuit; filter circuit; gain 32 dB; linearity requirements; power 1.3 mW; power consumption; size 65 nm; transfer function; voltage 1.2 V; voltage 1.6 mV; CMOS analogue integrated circuits; HF amplifiers; radio receivers; radiofrequency filters; transfer functions
English
2011 18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011
2011
Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on
9781457718458
2011
21
24
6122204
none
DE MATTEIS, M., Cocciolo, G., De Blasi, M., Baschirotto, A. (2011). A 1.3mW CMOS 65nm 4^th order 52dB-DR continuous-time analog filter for DVB-T receivers. In Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on (pp.21-24) [10.1109/ICECS.2011.6122204].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10281/36748
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