The potential of strained DOTFET technology is demonstrated. This technology uses a SiGe island as a stressor for a Si capping layer, into which the transistor channel is integrated. The structure information of fabricated samples is extracted from atomic force microscopy (AFM) measurements. Strain on the upper surface of a 30 nm thick Si layer is in the range of 0.7%, as supported by finite element calculations. The Ge content in the SiGe island is 30% on average, showing an increase towards the top of the island. Based on the extracted structure information, three-dimensional strain profiles are calculated and device simulations are performed. Up to 15% enhancement of the NMOS saturation current is predicted
Cervenka, J., Kosina, H., Selberherr, S., Zhang, J., Hrauda, N., Stangl, J., et al. (2011). Strained MOSFETs on ordered SiGe dots. SOLID-STATE ELECTRONICS, 65-66(1), 81-87 [10.1016/j.sse.2011.06.041].
Strained MOSFETs on ordered SiGe dots
VASTOLA, GUGLIELMO;MARZEGALLI, ANNA;MONTALENTI, FRANCESCO CIMBRO MATTIA;MIGLIO, LEONIDA
2011
Abstract
The potential of strained DOTFET technology is demonstrated. This technology uses a SiGe island as a stressor for a Si capping layer, into which the transistor channel is integrated. The structure information of fabricated samples is extracted from atomic force microscopy (AFM) measurements. Strain on the upper surface of a 30 nm thick Si layer is in the range of 0.7%, as supported by finite element calculations. The Ge content in the SiGe island is 30% on average, showing an increase towards the top of the island. Based on the extracted structure information, three-dimensional strain profiles are calculated and device simulations are performed. Up to 15% enhancement of the NMOS saturation current is predicted
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