Identifying and representing clusters of spatial defects in microelectronics planar artefacts

The aim of this work is to investigate the spatial structure of defectivity in integrated circuits fabrication. A prompt detection of an excess of defects and their spatial structure is critical for the entire fabrication process in order to limit yield loss. We propose first a control chart for spatial defectivity on the wafer area based on p-value. Then, a clustering procedure based on the minimum spanning tree algorithm is suggested to identify the areas of the wafer more prone to high defectivity and display their shape effectively.