A 28 nm CMOS-bulk lowpass analogue filter architecture is hereby proposed. The filter is based on an improved Active-Gm-RC structure, where both poles of a Miller-compensated operational amplifier (OPAMP) have been used for synthesising a third-order filter. Several well-known issues related to the 28 nm process node have been hereby mitigated by proper circuit/design techniques, enabling large signal-to-noise ratio (SNR) and 13.5 dBm IIP3. The proposed circuital solution performs 59 dB-SNR at 340 μW power consumption from a single 0.9 V supply-voltage. This allows one of the higher figure-of-merit (156 dB) in sub-1 V analogue filters state of the art.
De Matteis, M., Donno, A., D'Amico, S., Baschirotto, A. (2017). 0.9 V third-order 132 MHz single-OPAMP analogue filter in 28 nm CMOS. ELECTRONICS LETTERS, 53(2), 77-79 [10.1049/el.2016.3273].
0.9 V third-order 132 MHz single-OPAMP analogue filter in 28 nm CMOS
De Matteis, M
;Baschirotto, A
2017
Abstract
A 28 nm CMOS-bulk lowpass analogue filter architecture is hereby proposed. The filter is based on an improved Active-Gm-RC structure, where both poles of a Miller-compensated operational amplifier (OPAMP) have been used for synthesising a third-order filter. Several well-known issues related to the 28 nm process node have been hereby mitigated by proper circuit/design techniques, enabling large signal-to-noise ratio (SNR) and 13.5 dBm IIP3. The proposed circuital solution performs 59 dB-SNR at 340 μW power consumption from a single 0.9 V supply-voltage. This allows one of the higher figure-of-merit (156 dB) in sub-1 V analogue filters state of the art.
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