This paper presents a 28 nm-bulk-CMOS 3rd-order 132 MHz low-pass filter based on an improved Active-gm-RC stage. Challenges related to the design of analog circuits in 28 nm-bulk-CMOS process node are faced, mitigated and exploited by operating at both architecture and circuit design levels. The filter uses a single-opamp two-stage topology where both poles are used for synthesizing a 3rd-order low-pass transfer function. The proposed filter operates from a single 0.9 V supply voltage, consumes 340 µW and performs high linearity (IIP3 = 11.5 dBm at 21 and 22 MHz input tones) and large Signal-to-Noise ratio (58 dB). This enables one of the higher Figure-of-Merit (163.2 dB) with respect to the state-of-the-art.
D’Amico, S., De Matteis, M., Donno, A., Baschirotto, A. (2019). A 0.9 V 3rd-order single-opamp analog filter in 28 nm bulk-CMOS. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 98(1), 155-167 [10.1007/s10470-018-1261-y].
A 0.9 V 3rd-order single-opamp analog filter in 28 nm bulk-CMOS
De Matteis, Marcello;Baschirotto, Andrea
2019
Abstract
This paper presents a 28 nm-bulk-CMOS 3rd-order 132 MHz low-pass filter based on an improved Active-gm-RC stage. Challenges related to the design of analog circuits in 28 nm-bulk-CMOS process node are faced, mitigated and exploited by operating at both architecture and circuit design levels. The filter uses a single-opamp two-stage topology where both poles are used for synthesizing a 3rd-order low-pass transfer function. The proposed filter operates from a single 0.9 V supply voltage, consumes 340 µW and performs high linearity (IIP3 = 11.5 dBm at 21 and 22 MHz input tones) and large Signal-to-Noise ratio (58 dB). This enables one of the higher Figure-of-Merit (163.2 dB) with respect to the state-of-the-art.
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