To cope with the high trigger and data rates expected from the high-luminosity upgrade of the LHC (HL-LHC), the readout electronics of the Monitored Drift Tube (MDT) chambers of the ATLAS muon spectrometer has to be replaced. In addition, the data of the MDT detectors will be used for the first-level muon trigger to improve the muon transverse momentum resolution and reduce the overall trigger rate. A new trigger and readout system will be implemented which requires new time-to-digital converter (TDC) ASICs on the front-end boards to digitize the drift time measurements and transmit them in streamed mode to the off-detector first-level muon track trigger processors. For backward compatibility and test purposes, the chip also contains a trigger matching block and corresponding output format. A prototype of the new TDC chip has been designed and fabricated in TSMC 130 nm CMOS technology. The design, simulation and performance test results will be discussed.
Kroha, H., Abovyan, S., Danielyan, V., Fras, M., Kortner, O., Richter, R., et al. (2018). Design of a Time-to-Digital Converter ASIC for the ATLAS MDT Chambers at HL-LHC. Intervento presentato a: 2018 IEEE Nuclear Science Symposium and Medical Imaging Conference, Sydney, Australia.
Design of a Time-to-Digital Converter ASIC for the ATLAS MDT Chambers at HL-LHC
Baschirotto, AMembro del Collaboration Group
;De Matteis, MMembro del Collaboration Group
;Pipino, AMembro del Collaboration Group
;Resta, FMembro del Collaboration Group
;
2018
Abstract
To cope with the high trigger and data rates expected from the high-luminosity upgrade of the LHC (HL-LHC), the readout electronics of the Monitored Drift Tube (MDT) chambers of the ATLAS muon spectrometer has to be replaced. In addition, the data of the MDT detectors will be used for the first-level muon trigger to improve the muon transverse momentum resolution and reduce the overall trigger rate. A new trigger and readout system will be implemented which requires new time-to-digital converter (TDC) ASICs on the front-end boards to digitize the drift time measurements and transmit them in streamed mode to the off-detector first-level muon track trigger processors. For backward compatibility and test purposes, the chip also contains a trigger matching block and corresponding output format. A prototype of the new TDC chip has been designed and fabricated in TSMC 130 nm CMOS technology. The design, simulation and performance test results will be discussed.
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