An in-depth analysis of modern technologies could represent the base for the success of the High Luminosity Large Hadron Collider experiments. The requirement is a new reliable electronics in 1Grad-TID environments. For the purpose, single devices in TSMC 28 nm bulk CMOS technology have been realized and studied. Preliminary experimental results demonstrate nMOS structures more resistant than pMOS. Nevertheless, the considerable leakage current increment is not negligible because it could affect analog circuits as the pixel readout channel hereby presented. In the particular case, the high radiation level induces a gain reduction and a slowdown of the time response.

Resta, F., Gerardin, S., Mattiazzo, S., Paccagnella, A., De Matteis, M., Enz, C., et al. (2018). 1GigaRad TID impact on 28 nm HEP analog circuits. INTEGRATION, 63, 306-314 [10.1016/j.vlsi.2018.04.007].

1GigaRad TID impact on 28 nm HEP analog circuits

Resta, F.
Primo
;
De Matteis, M.;Baschirotto, A.
Ultimo
2018

Abstract

An in-depth analysis of modern technologies could represent the base for the success of the High Luminosity Large Hadron Collider experiments. The requirement is a new reliable electronics in 1Grad-TID environments. For the purpose, single devices in TSMC 28 nm bulk CMOS technology have been realized and studied. Preliminary experimental results demonstrate nMOS structures more resistant than pMOS. Nevertheless, the considerable leakage current increment is not negligible because it could affect analog circuits as the pixel readout channel hereby presented. In the particular case, the high radiation level induces a gain reduction and a slowdown of the time response.
Articolo in rivista - Articolo scientifico
28 nm bulk CMOS technology; Analog circuits; GigaRad; HEP experiments; Radiation;
Analog circuits; GigaRad; HEP experiments; Radiation; 28 nm bulk CMOS technology
English
2018
63
306
314
none
Resta, F., Gerardin, S., Mattiazzo, S., Paccagnella, A., De Matteis, M., Enz, C., et al. (2018). 1GigaRad TID impact on 28 nm HEP analog circuits. INTEGRATION, 63, 306-314 [10.1016/j.vlsi.2018.04.007].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10281/198053
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