The complete design and electrical characterization of a readout frontend for high luminosity pixel detectors is hereby presented. The design has been carried out in 28nm bulk-CMOS technology. The selected technology process shows significant advantages in terms of radiation hardness, faster/low-power digital signal processing and whole chip area reduction. Nonetheless, it is challenging in terms of operating point (0.9V supply voltage at 0.5V threshold voltage for standard process transistors), dynamic range, and large sensitivity to Process-Voltage-Temperature variations. The proposed integrated circuit includes the cascade of a low-noise preamplifier stage and a switched-capacitor inverter-based comparator. The overall system detects input charges up to 14fC and provides information about the amount of the charge with a Time-over-Threshold (ToT) technique. It features 4.3μW power consumption, 54dB Signal Noise Ratio and 0.02mm2 area occupancy. A ToT range of 180ns in 28nm bulk-CMOS represents a challenge for the future Time-to-Digital Converters (TDC) used in High-Energy-Physics readout systems. Analog front-end and TDC development anticipate a higher charge quantization resolution in the next physics experiments.
Resta, F., Pipino, A., Pezzotta, A., DE MATTEIS, M., Croce, M., Baschirotto, A. (2017). A 4.3μW 28nm-CMOS pixel front-end with switched inverter-based comparator. In SENSORS, 2016 IEEE. Institute of Electrical and Electronics Engineers Inc. [10.1109/ICSENS.2016.7808899].
A 4.3μW 28nm-CMOS pixel front-end with switched inverter-based comparator
RESTA, FEDERICA;PIPINO, ALESSANDRA;PEZZOTTA, ALESSANDRO;DE MATTEIS, MARCELLO;BASCHIROTTO, ANDREA
2017
Abstract
The complete design and electrical characterization of a readout frontend for high luminosity pixel detectors is hereby presented. The design has been carried out in 28nm bulk-CMOS technology. The selected technology process shows significant advantages in terms of radiation hardness, faster/low-power digital signal processing and whole chip area reduction. Nonetheless, it is challenging in terms of operating point (0.9V supply voltage at 0.5V threshold voltage for standard process transistors), dynamic range, and large sensitivity to Process-Voltage-Temperature variations. The proposed integrated circuit includes the cascade of a low-noise preamplifier stage and a switched-capacitor inverter-based comparator. The overall system detects input charges up to 14fC and provides information about the amount of the charge with a Time-over-Threshold (ToT) technique. It features 4.3μW power consumption, 54dB Signal Noise Ratio and 0.02mm2 area occupancy. A ToT range of 180ns in 28nm bulk-CMOS represents a challenge for the future Time-to-Digital Converters (TDC) used in High-Energy-Physics readout systems. Analog front-end and TDC development anticipate a higher charge quantization resolution in the next physics experiments.
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
